The present invention relates to the direct digital synthesis of sinusoidal signals, and more directly to a frequency dither technique for reducing phase modulation errors made in the use of a direct digital synthesizer (DDS) to generate a reference frequency.
A DDS is a very convenient and well known means of generating sinusoidal waves with very fine frequency resolution and stable average frequency. A typical DDS has an accumulator having as an input a phase increment and a feedback value from a phase register and having as an output an accumulated phase value for storing in the phase register. The output from the phase register also is truncated and applied as an address to a SIN( ) lookup table to generate a series of digital values that, when converted to an analog signal by a digital-to-analog converter, results in a sinusoidal waveform at a desired frequency determined by the phase increment value. The use of a DDS has been limited by artifacts in the output due to quantization errors implicit in its very nature. The major limit to the spectral purity of a DDS generated signal is the phase quantization due to the SIN( ) lookup table having a limited number of entries. Typically the phase accumulator and register contain 32 bits. However only 12 of these may be passed on to the SIN( ) lookup table. The result of this is a sawtooth waveform of phase error having a magnitude of 2xe2x88x9212 cycles of the generated rate. This may cause significant spurs in the output spectrum of the generated reference frequency.
One way to reduce the effect of spurs is to lock the DDS to another oscillator, typically a voltage controlled oscillator (VCO) in a phase locked loop (PLL) with a bandwidth smaller than the closest spur generated by the truncation process. This attenuates spurs outside the loop bandwidth of the PLL. This also has the useful feature of upconverting the DDS output to a higher frequency if desired, as is typical. Unfortunately the spurs for certain generated frequencies still fall within the loop bandwidth and are not attenuated. Application Note AN2334-4, pages 24-25, from QUALCOMM Incorporated, VLSI Products Division of San Diego, Calif. shows how to calculate the location of the spurs.
Another way to reduce the effect of spurs, as described in IEEE Transactions on Communications, Vol. 43, No. 7, July 1995 at pages 2254-2262 by Flanagan and Zimmerman xe2x80x9cSpur-Reduced Digital Sinusoid Synthesisxe2x80x9d, is through the use of a pseudorandom number (PRN) sequence applied to the phase and amplitude quantizer. This technique allows a general reduction in spurs, but with a rather slow improvement rate.
What is desired is a technique for reducing spurs caused by phase quantization in a DDS.
Accordingly the present invention uses frequency dithering for achieving DDS spectral purity. The location of spurs is located and nothing is done if the spurs fall outside of the loop bandwidth of an external PLL. However if the spurs fall within the loop bandwidth, the output frequency is generated by the generation of two frequencies on either side of a desired output frequency so that their average frequency equals the desired output frequency. These output frequencies have the property that their spurs fall outside the PLL loop bandwidth.
The objects, advantages and other novel features of the present invention are apparent from the following detailed description when read in conjunction with the appended claims and attached drawing.